Dagstuhl Seminar 17061
Wildly Heterogeneous Post-CMOS Technologies Meet Software
( Feb 05 – Feb 10, 2017 )
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Organizers
- Jerónimo Castrillón-Mazo (TU Dresden, DE)
- Tei-Wei Kuo (National Taiwan University - Taipei, TW)
- Heike E. Riel (IBM Research Zurich, CH)
- Sayeef Salahuddin (University of California - Berkeley, US)
Contact
- Annette Beyer (for administrative matters)
The end of exponential scaling in conventional CMOS technologies has been forecasted for many years by now. While advances in fabrication made it possible to reach limits beyond those predicted, the so anticipated end seems to be imminent today. An indication of this is the research boom, both in academia and industry, in emerging technologies that could complement or even replace CMOS devices. This seminar seeks to discuss bridges between material research, hardware components and, ultimately, software for information processing systems. Given a new class of wildly heterogeneous systems that integrate different technologies, we want to reason about enabling hardware and software abstractions, from languages and system-software down to hardware mechanisms. A prominent example of abstractions that made new technologies viable is the flash translation layer for flash storage. The challenge of realizing an efficient wildly heterogeneous system can only be tackled by employing holistic and synergistic approaches in an interdisciplinary environment. This requires building the bridges from materials to software via suitable abstractions and interfaces for interactions between different layers.
There is a broad range of emerging technologies, each bearing deep technical and economic complexities. Thus, it is difficult for isolated initiatives to build bridges from materials to software. We therefore want to bring together computer scientists with experts in emerging technologies. In particular, the seminar is structured around four partially overlapping areas, namely: (i) far-fetched materials and physics such as spin, nanomagnets, phase transition, and correlated phenomena, (ii) near future materials (and software) such as phase-change memory, nanowires, nanotubes, and neuromorphic devices, (iii) low-level software layers for new technologies such as runtime support, middleware, and HW/SW-co-designed firmware, and (iv) upper software layers such as new programming/specification languages, models, and software synthesis.
Important questions addressed by the seminar include the following:
- Materials/Devices: What are the current status and the roadmap of post-CMOS materials and technologies? What will be the expected characteristics of the new devices? Will new technologies enable a fundamentally different computing paradigm, e.g., beyond von-Neumann? What are the challenges for proper benchmarking of different technologies?
- Hardware/Software Stack: How much of the hardware's heterogeneity and its characteristics should be exposed to programmers? How general may be a programming model/language for future (yet unknown) hardware? How to make software adapt itself to hardware with fluctuating resources? Which new applications can be enabled by emerging materials and technologies and what needs to be done at the software layers to make them viable?
- Analysis: How can we model the interactions across the layers of the hardware/software stack? What kind of formal operational models and analysis methods are needed for evaluating heterogeneous systems? Can system- level analysis of new technologies give insights to material scientists, disrupting the otherwise incremental innovation paradigm?
The main goal of the seminar is to close the gap between basic research on computing technologies and software. By bringing together experts from the individual fields and also researchers working interdisciplinarily across the fields, the seminar aims to foster a mutual understanding about the challenges of advancing computing beyond current CMOS technology: Researchers from the software domain will get insights into upcoming technologies and how state-of-the- art techniques can be leveraged for future systems, while electrical engineers will get a better understanding about the software requirements and the potential novel hardware may have for new software applications. In interdisciplinary discussions we also wish to create long-term visions about a future hardware/software stack to prepare the path for big leaps in adoption of novel materials for computing. We expect the seminar to be a seed for international collaborations among the attendees.
Creative Commons BY 3.0 DE
Jerónimo Castrillón-Mazo, Tei-Wei Kuo, Heike E. Riel, and Sayeef Salahuddin
Topic and Structure
The end of exponential scaling in conventional CMOS technologies has been forecasted for many years by now. While advances in fabrication made it possible to reach limits beyond those predicted, the so anticipated end seems to be imminent today. An indication of this is the research boom, both in academia and industry, in emerging technologies that could complement or even replace CMOS devices. Examples for such emerging technologies include tunnel FETs, nonvolatile memories such as magnetoresistive RAM, 3D integration, carbon nanotube transistors, and graphene.
The main goal of this seminar was to discuss bridges between material research, hardware components and, ultimately, software for information processing systems. Given a new class of wildly heterogeneous systems that integrate different technologies, we want to reason about enabling hardware and software abstractions, from languages and system-software down to hardware mechanisms. The challenge of realizing an efficient wildly heterogeneous system can only be tackled by employing holistic and synergistic approaches in an interdisciplinary environment. By bringing together experts from the individual fields and also researchers working interdisciplinarily across fields, the seminar helped to foster a mutual understanding about the challenges of advancing computing beyond current CMOS technology and to create long-term visions about a future hardware/software stack.
The seminar was structured around four partially overlapping areas, namely: (i) far-fetched materials and physics such as spin, nanomagnets, phase transition, and correlated phenomena, (ii) near future materials (and software) such as phase-change memory, nanowires, nanotubes, and neuromorphic devices, (iii) low-level software layers for new technologies such as operating systems, runtime support, middleware, and HW/SW-co-designed firmware, and (iv) upper software layers such as new programming/specification languages, models, and software synthesis.
Important questions addressed by the seminar included:
- Materials/Devices: What are the current status and the roadmap of post-CMOS materials and technologies? What will be the expected characteristics of the new devices? Will new technologies enable a fundamentally different computing paradigm, e.g., beyond von Neumann? What are the challenges for proper benchmarking of different technologies?
- Hardware/Software Stack: How much of the hardware's heterogeneity and its characteristics should be exposed to programmers? How general may be a programming model/language for future (yet unknown) hardware? How to make software adapt itself to hardware with fluctuating resources? Which new applications can be enabled by emerging materials and technologies and what needs to be done at the software layers to make them viable?
- Analysis: How can we model the interactions across the layers of the hardware/software stack? What kind of formal operational models and analysis methods are needed for evaluating heterogeneous systems? Can system-level analysis of new technologies give insights to material scientists, disrupting the otherwise incremental innovation paradigm?
Main Conclusions
Summary
There will probably be no CMOS replacement for chips with billions of transistors in the next 20 years, but architectural advances at various levels (such as 3D transistors, 3D integration of memory and logic, specialization, and reconfigurability) will lead to performance improvements despite the scaling limitations of planar CMOS technology. New non-volatile memories (e.,g., spin-based) bear the potential to radically change various areas of computing, such as data-intensive processing and neuromorphic computing. New hardware architectures will need rethinking today's software stack and our widely used programming models. Finally, even though some post-CMOS technologies will not replace high-end CMOS transistors, there is great potential in new, yet unknown, applications. Applications, backed by a strong commercial demand, will give some technologies the push to become viable. Examples are radio-frequency for carbon nanotubes, graphene based sensors, organic low-cost transistors for wearables, and memristors for neuromorphic computing.
Post-CMOS logic for compute-intensive applications
Currently, there is no alternative to CMOS on the horizon to realize logic for large von Neumann computing, due to lower projected performance and/or yield challenges. Candidates discussed on the seminar have been: tunnel FETs, III-V, 2D materials such as graphene, CNTs, or spintronics. This means that general purpose and high-performance computing will most probably be based on CMOS in the medium term. To workaround the CMOS scaling problem, architectural specialization will gain more and more importance leading to general purpose computing systems with (various) specialized accelerators. We already find them today in, e.,g., mobile devices or GPU high-performance computing accelerators. Additionally, reconfigurable logic, such as FPGAs, and application-specific circuits have a high potential for performance gains. However, it is a big challenge to program such heterogeneous systems. Work towards solutions based on dataflow programming, memory access patterns, skeletons, and domain-specific languages have been discussed at the seminar. Additionally, operating system might need to adapt to allow, for example, accelerators to perform system calls.
Emerging memory technologies
In near future, new non-volatile memories will be available that could unify RAM and permanent storage, including MRAM and RRAM. While these could provide huge benefits for memory-intensive applications, the implications on architecture and software stack are not yet clear. For example, what will be the role of the file system in such an architecture? And how to deal with security aspects when every bit in RAM is permanent? Looking further into the future, the spin-based, non-volatile racetrack memory has the potential to compete with SRAM in terms of performance, while consuming considerably less energy. High-performance and energy-efficient non-volatile memories will also be important for neuromorphic devices.
Going 3D
3D integration enables the integration of heterogeneous technologies for logic, memory, communication, and sensing on a single chip. At the transistor level, 3D corrugated transistors were discussed as a promising direction to keep reducing the footprint while avoiding short-channel effects. Advancing today's die stacking technology through fine-grained vias linking the layers, will provide a substantial improvement for latencies and bandwidths in the systems. Bringing memory closer to logic will lower the memory wall (or even lead to a breakdown?). This means that many existing applications could be compute bound (again) and the processor architecture could be potentially simplified by removing the overhead that was added to workaround the memory wall, such as big caches and prefetchers, making place for additional compute units. In this optimistic scenario, general-purpose computing would receive a great (one-time) performance boost. For compilers and applications, we would have to rethink our way of optimizing code.
Computing beyond von Neumann
Architectural approaches beyond von Neumann were also discussed to speedup specific applications. Examples were neuromorphic computers, analog circuits, and dataflow machines. Of course these approaches cannot replace general purpose processors completely. A possible future architecture would combine classical von Neumann processors with non-von Neumann accelerators (on the same chip) to enable mixed programming. The recent industry adoption of machine learning drives the need for neuromorphic computers. While these systems already outperform general purpose processors today, new technologies such as non-volatile memories and analog spintronics promise even greater gains. Promising analog circuits were shown to perform well for concrete NP-complete problems such as SAT and graph coloring. Along these lines, a theoretical framework was introduced that may serve to abstractly compare the asymptotic energy efficiency between the analog and the digital realizations of a system. Finally, dataflow machines where discussed that stream data directly between computational units without the overhead of registers and caches, thereby removing the "Turing tax".
Special applications
Some of the materials considered in the seminar are very likely not able to compete with CMOS for logic, but have strengths in other electronic application areas such as sensors, radio frequency, and displays. Carbon nanotubes and graphene are promising materials for high-frequency antennas required for upcoming wireless communication systems. In the particular case of Graphene, it seems that the initial technological hype has passed, and engineering has taken over to produce new clever devices (e.g., nano-membranes for sensing). Organic electronics are already commercially available in displays and OLEDs. Their distinct features of flexibility, low production cost (printed electronics), and biodegradability could potentially open completely new application areas for logic, but not at comparable speed and efficiency to CMOS. These devices have also been deemed important for bio-compatibility. However, there is a long road ahead for testing and certifying actual devices in living tissue, which is not a trivial task, considering the wealth of molecules being investigated in this domain.
Co-design and design space exploration
Proper hardware/software co-design will be very important to achieve performance gains given the limits of CMOS and the prospective wildly heterogeneous and/or application-specific computing systems. Given a specific application problem, numerous implementation alternatives, from the algorithm down to the hardware architecture and technologies, might be feasible. Tools that help developers navigating the huge design space (e.g., using modeling and benchmarking techniques) and automate an efficient implementation as much as possible are needed. It appears to be that the large part of the software is less flexible than the hardware and much work has to be done to make software future-proof.
Jerónimo Castrillón-Mazo, Tei-Wei Kuo, Heike E. Riel, Sayeef Salahuddin, and Matthias Lieber
- Rehan Ahmed (ETH Zürich, CH) [dblp]
- Stefano Ambrogio (IBM Almaden Center - San Jose, US) [dblp]
- Nils Asmussen (TU Dresden, DE) [dblp]
- Tal Ben-Nun (The Hebrew University of Jerusalem, IL) [dblp]
- Jerónimo Castrillón-Mazo (TU Dresden, DE) [dblp]
- Jian-Jia Chen (TU Dortmund, DE) [dblp]
- Yiran Chen (Duke University - Durham, US) [dblp]
- Martin Claus (TU Dresden, DE) [dblp]
- Ayse Coskun (Boston University, US) [dblp]
- Suman Datta (University of Notre Dame, US) [dblp]
- Erik P. DeBenedictis (Sandia National Labs - Albuquerque, US) [dblp]
- Gianluca Fiori (University of Pisa, IT) [dblp]
- Shunsuke Fukami (Tohoku University, JP) [dblp]
- Balazs Gerofi (RIKEN - Kobe, JP) [dblp]
- Sebastian Hack (Universität des Saarlandes, DE) [dblp]
- Xiaobo Sharon Hu (University of Notre Dame, US) [dblp]
- Paul H. J. Kelly (Imperial College London, GB) [dblp]
- Christoph W. Kessler (Linköping University, SE) [dblp]
- Tei-Wei Kuo (National Taiwan University - Taipei, TW) [dblp]
- Roland Leißa (Universität des Saarlandes, DE) [dblp]
- Max Lemme (Universität Siegen, DE)
- Matthias Lieber (TU Dresden, DE) [dblp]
- Michael Niemier (University of Notre Dame, US) [dblp]
- Stuart Parkin (MPI - Halle, DE) [dblp]
- Andy D. Pimentel (University of Amsterdam, NL) [dblp]
- Sebastian Reineke (TU Dresden, DE)
- Heike E. Riel (IBM Research Zurich, CH) [dblp]
- Mark Rodwell (University of California - Santa Barbara, US)
- Eleonora Testa (EPFL - Lausanne, CH) [dblp]
- Marcus Völp (University of Luxembourg, LU) [dblp]
Classification
- hardware
- operating systems
- programming languages / compiler
Keywords
- Hardware/Software Co-Design
- Nanoelectronics
- Emerging Post-CMOS Circuit Materials and Technologies
- Heterogeneous Hardware
- System Architecture
- Operating Systems
- Runtime Support
- Compilers
- Programming Languages
- Formal Methods
