Dagstuhl-Seminar 19141
Programmable Network Data Planes
( 31. Mar – 05. Apr, 2019 )
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Organisatoren
- Gianni Antichi (Queen Mary University of London, GB)
- Theophilus Benson (Brown University - Providence, US)
- Nate Foster (Cornell University, US)
- Fernando M. V. Ramos (University of Lisbon, PT)
- Justine Sherry (Carnegie Mellon University - Pittsburgh, US)
Kontakt
- Shida Kunz (für wissenschaftliche Fragen)
- Simone Schilke (für administrative Fragen)
Impacts
- Full-stack SDN : The Next Big Challenge? article in SOSR '20 : Proceedings of the Symposium on SDN Research : March 2020 : Pages 48–54 - Antichi, Gianni; Retvari, Gabor - New York : ACM, 2020..
- The Programmable Data Plane : Abstractions, Architectures, Algorithms, and Applications : article - Michel, Oliver; Bifulco, Roberto; Retvari, Gabor; Schmid, Stefan - New York : ACM, 2021. - 36 pp. - (ACM computing surveys ; 54. 2021, 4, Article 82).
Over the past 10 years, Software-Defined Networking (SDN) has facilitated the development of a variety of novel control-plane abstractions, but its adoption has been limited by poor support for programmability in existing data planes. For example, the OpenFlow specification evolved over time to support different operator requirements, growing from 12 protocols in the original version to nearly 50 protocols in later versions. Recent advances in the design of switch ASICS, FPGAs, smart NICs, and middleboxes have shown that it is possible to build data planes that combine rich programmability and good performance.
The goal of this seminar is to bring together the researchers and practitioners from the areas of networking, systems, programming languages, verification, and hardware, to discuss the present and future of programmable network data planes. We plan to explore questions such as:
- What is the right division of labour between control and data plane?
- Where should packet-processing functionality reside?
- What are the right high-level language abstractions required to program them?
- How should programmable data planes evolve?
- How can networks benefit from these new elements?
- Are there trade-offs between programmability, performance, and security?
To try to answer these questions, we plan to discuss various topics during the seminar, including data plane architectures, programming languages, compilers and targets, use cases and applications, formal methods and verification tools, end-system issues, among others.
Creative Commons BY 3.0 DE
Gianni Antichi, Theophilus Benson, Nate Foster, Fernando M. V. Ramos, and Justine Sherry
Traditional networks are complex and hard to manage. It is difficult to configure networks according to predefined policies, and to reconfigure them in response to dynamic changes. Traditional networks are also vertically integrated: the control and data planes are bundled together. Around 10 years ago, the Software-Defined Networking (SDN) paradigm emerged and began to change this state of affairs. SDN breaks the vertical integration, separating the network's control logic from the underlying routers and switches (by means of a protocol such as OpenFlow) and promoting the (logical) centralization of network control. As such, it enabled the introduction of new abstractions in networking giving the ability to program the control plane of networks. Modern data center networks employ SDN-based techniques to simplify network management and operate at very large scale, and new networking services are now made possible - prominent examples are VMware's Network Virtualization Platform, Google's Andromeda and Microsoft's AccelNet.
Despite offering programmatic control to network operators, the original SDN data plane was limited to the protocols supported by OpenFlow. Over time, the OpenFlow specification evolved to support operator requirements, growing from 12 header fields in the original version to nearly 50 protocols in recent versions. The primary reason that OpenFlow is limited to specific "baked in" protocols is that the capabilities of switching chips are fixed at fabrication time. However, recent chip designs have demonstrated that it is possible to increase the flexibility of switch ASICs while still maintaining the terabit speeds required of networking hardware. In addition, as programming these chips is difficult - they expose their own low-level interface, akin to microcode programming - a domain-specific language, P4, was recently proposed to program network data planes (see p4.org). These advances are leading to a growing understanding of the inherent challenges related to data plane programming, resulting in further changes that promote future advances. For example, P4 was originally based on a simple architectural model, but has evolved to allow different switch architectures, aiming for stability of the language while increasing the flexibility to switch designers.
At the same time as programmable switches and programming languages such as P4 were being developed, a different group of researchers within the networking community has explored an alternative approach in which advanced data plane functionality is implemented on end hosts. This approach is often known as Network Function Virtualization (NFV). Platforms such as OpenVSwitch and Intel's DPDK framework make it possible to implement sophisticated packet-processing functions on end hosts rather than network switches, at line rates up to 10Gb/s and beyond. A key advantage of using CPUs is their flexibility, which makes it easy to adapt as requirements evolve. For example, it is straightforward to implement fine-grained monitoring of network flows or cryptographic operations - two pieces of functionality that are difficult to implement on standard switch ASICs.
In this context, the seminar on programmable data planes brought together leading practitioners from the areas of networking, systems, programming languages, verification, and hardware, to exchange ideas about important problems and possible solutions, and to begin the task of developing a research agenda related to programmable data planes. We have discussed several topics, including data plane architectures; programming languages, compilers and targets; use cases and applications; verification tools and formal methods; and end-system issues.
In the seminar we discussed questions including where packet-processing functionality should reside, how programmable data planes should evolve, how networks can benefit from these new elements, and how they can cope with the new challenges that arise. The focus was on the key challenges of the field and on the most fundamental problems to look at in the next 10 years, together with an aim to identify the "right" steps to take to move forward and the key problems to tackle next.
We have made some progress toward answering the following synergistic research questions during the seminar: What is the right division of labor between control and data plane? What are the right high-level language abstractions for programming networks, and what uarantees could we expect a compiler to provide reachability, security, or even properties as detailed as the correct use of cryptography? What is the trade-off between making more intelligent data plane architectures and the resulting network performances? Can we enhance current methods adopted to check network configuration errors with new solutions that automatically assure the absence of misconfiguration?
In the rest of the report we summarise the outcome of the most relevant discussions we had during the seminar.
Gianni Antichi, Theophilus Benson, Nate Foster, Fernando M. V. Ramos, and Justine Sherry
- Gianni Antichi (Queen Mary University of London, GB) [dblp]
- Mario Baldi (Polytechnic University of Torino, IT) [dblp]
- Sujata Banerjee (VMware - Palo Alto, US) [dblp]
- Theophilus Benson (Brown University - Providence, US) [dblp]
- Roberto Bifulco (NEC Laboratories Europe - Heidelberg, DE) [dblp]
- Gordon Brebner (Xilinx - San José, US) [dblp]
- Marco Chiesa (KTH Royal Institute of Technology - Stockholm, SE) [dblp]
- Paolo Costa (Microsoft Research - Cambridge, GB) [dblp]
- Jon Crowcroft (University of Cambridge, GB) [dblp]
- Lars Eggert (NetApp Finland Oy, FI) [dblp]
- Anja Feldmann (MPI für Informatik - Saarbrücken, DE) [dblp]
- Andy Fingerhut (CISCO Systems - San Jose, US) [dblp]
- Nate Foster (Cornell University, US) [dblp]
- Soudeh Ghorbani (Johns Hopkins University - Baltimore, US) [dblp]
- Timothy G. Griffin (University of Cambridge, GB) [dblp]
- Stephen Ibanez (Stanford University, US) [dblp]
- Changhoon Kim (Barefoot Networks - Palo Alto, US) [dblp]
- Daehyeok Kim (Carnegie Mellon University - Pittsburgh, US) [dblp]
- Eder L. Fernandes (Queen Mary University of London, GB) [dblp]
- Alberto Lerner (University of Fribourg, CH) [dblp]
- Dotan Levi (Mellanox Technologies Ltd. -Yokenam, IL)
- Nick McKeown (Stanford University, US) [dblp]
- Aurojit Panda (New York University, US) [dblp]
- Justin Pettit (VMware - Palo Alto, US) [dblp]
- Ben Pfaff (VMware - Palo Alto, US) [dblp]
- Salvatore Pontarelli (University of Rome "Tor Vergata", IT) [dblp]
- Costin Raiciu (University Politehnica of Bucharest, RO) [dblp]
- Fernando M. V. Ramos (University of Lisbon, PT) [dblp]
- Gábor Rétvári (Budapest University of Technology & Economics, HU) [dblp]
- Hugo Sadok (Federal University of Rio de Janeiro, BR) [dblp]
- Justine Sherry (Carnegie Mellon University - Pittsburgh, US) [dblp]
- Salvatore Signorello (University of Lisbon, PT) [dblp]
- Alexandra Silva (University College London, GB) [dblp]
- Robert Soulé (University of Lugano, CH) [dblp]
- Alex Sprintson (Texas A&M University - College Station, US) [dblp]
- David L. Tennenhouse (VMware - Palo Alto, US) [dblp]
- Laurent Vanbever (ETH Zürich, CH) [dblp]
- Stefano Vissicchio (University College London, GB) [dblp]
- David Walker (Princeton University, US) [dblp]
- Hakim Weatherspoon (Cornell University, US) [dblp]
- Minlan Yu (Harvard University - Cambridge, US) [dblp]
- Noa Zilberman (University of Cambridge, GB) [dblp]
Klassifikation
- hardware
- networks
- programming languages / compiler
Schlagworte
- networks
- Programmable data planes
- programming languages
- network verification
